About Event

🚀 ChipCraft 2.0 – 24hr VLSI Design Hackathon 🚀

📅 13–14 March 2026 | 🏛️ DSPSD Lab 321, Kalasalingam University, Krishnankoil
🎯 *Theme: RTL to Synthesis + Formal Verification

Challenge:
Given a real‑world problem statement, design an optimized RTL solution, synthesize to netlist, and verify using formal methods—all within 24 hours!

What you'll do:
- RTL coding (Verilog/SystemVerilog)
- Logic synthesis with Synopsys Design Compiler
- Formal verification with Synopsys VC Formal
- Generate timing/area reports and present your chip

Powered by: Synopsys Chips to Startup (C2S) Program + KARE IEEE EDS/SSCS

Team: 2–3 members
Fee: ₹300/person
Prizes: ₹25,000 pool (₹15k/₹7k/₹3k)
Register: [euphoria.kalasalingam.ac.in/register](https://euphoria.kalasalingam.ac.in)

Who should join: ECE/EEE/CSE students with basic Verilog + Linux skills. Some prior Synopsys experience required—training provided!

Why ChipCraft? Hands‑on industry VLSI flow = direct path to semiconductor jobs (RTL/DFT/PD roles).

#VLSI #ChipDesign #Hackathon #Synopsys #IEEEEDS